Skip to content
CadHut

CadHut

FPGA and Circuit Design

  • News
  • Articles
  • FPGA
    • Xilinx
    • Intel (Altera)
    • Lattice
    • MicroSemi
  • About
    • About Us
    • MeetUp Group

Category: Articles

Converting VHDL to Verilog

Posted by Iain Waugh on 14 August, 202222 August, 2022 in Articles, Verilog, VHDL

Most open source tools don’t accept VHDL as an input, which is a real shame/annoyance if VHDL is your thing. What are the options?

How To Install OpenROAD And Other VLSI Tools Under Ubuntu 22.04 Or Linux Mint 21

Posted by Iain Waugh on 7 August, 202219 December, 2022 in Articles, ASIC, HowTo, Intermediate, VHDL

This HowTo will take you from a blank/brand new install of Ubuntu 22.04 or Linux Mint 21 up to the point where you can run OpenROAD to make a GDS-II file of a design.

Sydney FPGA ASIC March 2022 Meeting Slides

Posted by Iain Waugh on 3 March, 2022 in Articles, ASIC, Beginners, Digital Logic, FPGA

Here is the slide deck used for the “Trends” presentation: And here is the slide deck used for the AXI presentation:

Emacs Logo

Installing Emacs For VHDL Work

Posted by Iain Waugh on 27 September, 20207 August, 2022 in Articles, Beginners, HowTo, Intermediate, VHDL

This article shows you how to set up Emacs for VHDL work and make it behave like a regular Windows text editor

How To Install Vivado/Vitis Using Just The Command-Line

Posted by Iain Waugh on 8 September, 20209 August, 2022 in Advanced, Articles, HowTo, Intermediate

Can Vivado/Vitis be installed without using the GUI installer? Fortunately, the answer is “yes”.

How To Set Up And Use MSys2

Posted by Iain Waugh on 2 August, 20207 July, 2021 in Articles, Beginners, HowTo

Windows developers often need to use Unix-style commands and build software binary executables from source code.
This article shows you how to install MSys2 and how to use it for development.

How To Read VHDL Code

Posted by Iain Waugh on 26 July, 20207 July, 2021 in Articles, Beginners, HowTo, VHDL

HDL languages like VHDL and Verilog are not like normal programming languages. This post describes how to read VHDL code and synthesise it in your head.

Categories

  • Advanced
  • Articles
  • ASIC
  • Beginners
  • Digital Logic
  • FPGA
  • HowTo
  • Intermediate
  • News
  • RISC-V
  • Signal Integrity
  • Verilog
  • VHDL
Copyright © 2023 CadHut. All Rights Reserved.
Fashify Theme by FRT