Microchip has announced the first FPGA to have a hard RISC-V IP CPU core; the PolarFire SoC. Read on to find out more.
Author: Iain Waugh
IBM announced its open-source A2O POWER core (that’s a capital “o”, not a zero), joining the A2I core it opened on the 30th of June.
Here is the slide deck I used during the Austin TX FPGA meeting.
Can Vivado/Vitis be installed without using the GUI installer? Fortunately, the answer is “yes”.
TerosHDL have announced a beta of their plugin for Visual Studio Code.
The annual Hot Chips conference is a place where industry and academia meet to discuss the latest developments in silicon chip technology. Head over to Anandtech and take a look at their coverage of the 2020 conference that’s on just…
There are 4 issues with Vivado 2020.1 that may affect your designs. A tactical patch has been created to avoid these issues.
This year, SkyWater announced a collaboration with Google to provide a service where you can design your own custom ASIC and get them for free (!!!). This week, Mohamed Shalan discussed the progress that’s being made for the individual steps…
Windows developers often need to use Unix-style commands and build software binary executables from source code.
This article shows you how to install MSys2 and how to use it for development.
SiFive have updated their RISC-V IP Portfolio with the release of the SiFive 20G1 range, offering FreeRTOS support, SiFive Shield security additions, lower power, better performance, smaller logic size and several other additions. Read the announcement here. Drew Barbier from…