Converting VHDL to Verilog

-------------------------------------------------------------------------------
--
-- Copyright (c) 2022 Iain Waugh. All rights reserved.
-- 
-- This code is a sample and does not come with any warranty or guarantee of correctness.
-- Redistribution and use in source and binary forms (with or without
-- modification) is permitted.
--
-------------------------------------------------------------------------------
-- Project Name  : Test Project
-- Author(s)     : Iain Waugh
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder is
  port(
    -- Clock and Reset signals
    clk : in std_logic;
    rst : in std_logic;

    i_data_a : in unsigned(7 downto 0);
    i_data_b : in unsigned(7 downto 0);

    o_data   : out unsigned(7 downto 0)
    );
end adder;

architecture adder_rtl of adder is

begin -- adder_rtl

  process (clk)
  begin
    if rising_edge(clk) then
      if (rst = '1') then
        o_data <= (others => '0');
      else
        o_data <= i_data_a + i_data_b;
      end if;
    end if;
  end process;

end adder_rtl;

ghdl -a adder.vhd
# Creates a file called 'work-obj93.cf'
ghdl synth --out=verilog adder > adder_ghdl.v

module adder
  (input  clk,
   input  rst,
   input  [7:0] i_data_a,
   input  [7:0] i_data_b,
   output [7:0] o_data);
  wire [7:0] n4_o;
  wire [7:0] n6_o;
  reg [7:0] n9_q;
  assign o_data = n9_q;
  /* adder.vhd:41:28  */
  assign n4_o = i_data_a + i_data_b;
  /* adder.vhd:38:7  */
  assign n6_o = rst ? 8'b00000000 : n4_o;
  /* adder.vhd:37:5  */
  always @(posedge clk)
    n9_q <= n6_o;
endmodule

cd ~/Work/vlsi/tools && git clone https://github.com/ldoolitt/vhd2vl
cd vhd2vl/src
make
sudo cp vhd2vl /usr/local/bin

vhd2vl adder.vhd > adder_vhd2vl.v

// File adder.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
// vhd2vl settings:
//  * Verilog Module Declaration Style: 2001

// vhd2vl is Free (libre) Software:
//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
//     http://www.ocean-logic.com
//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
//   Modifications (C) 2010 Shankar Giri
//   Modifications Copyright (C) 2002-2017 Larry Doolittle
//     http://doolittle.icarus.com/~larry/vhd2vl/
//   Modifications (C) 2017 Rodrigo A. Melo
//
//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
//   Verilog for correctness, ideally with a formal verification tool.
//
//   You are welcome to redistribute vhd2vl under certain conditions.
//   See the license (GPLv2) file included with the source for details.

// The result of translation follows.  Its copyright status should be
// considered unchanged from the original VHDL.

//-----------------------------------------------------------------------------
//
// Copyright (c) 2022 Iain Waugh. All rights reserved.
// 
// This code is a sample and does not come with any warranty or guarantee of correctness.
// Redistribution and use in source and binary forms (with or without
// modification) is permitted.
//
//-----------------------------------------------------------------------------
// Project Name  : Test Project
// Author(s)     : Iain Waugh
//-----------------------------------------------------------------------------
// no timescale needed

module adder(
input wire clk,
input wire rst,
input wire [7:0] i_data_a,
input wire [7:0] i_data_b,
output reg [7:0] o_data
);

// Clock and Reset signals




  // adder_rtl
  always @(posedge clk) begin
    if((rst == 1'b1)) begin
      o_data <= {8{1'b0}};
    end
    else begin
      o_data <= i_data_a + i_data_b;
    end
  end


endmodule