Today, SiFive announced a $1 Billion partnership with Intel, where SiFive will use their flexible customisation platform to support Intel Foundry Services and create Risc-V core that are optimised for Intel’s foundry platforms. SiFive has partnered with IFS to develop…
Author: Iain Waugh
Vivado 2021.1 came out at the end of last month. What’s new besides the name-change? Read on…
The International Symposium for FPGA 2021 was held last week. If you couldn’t make it to the virtual conference, here’s where to find the papers.
Alex Forencich has posted a livestream video to YouTube which nicely introduces CocoTB and demonstrates what it’s good for and how to use it. Click through for the video.
Xilinx released their latest release of the Vivado and Vitis tools yesterday.
AMD will acquire Xilinx in an all-stock transaction valued at $35 billion.
Intel have released Quartus Prime Pro 20.3.
There is a new family of radiation-hardened FPGAs from a French company, called NanoXplore. These parts are being evaluated for space applications be CERN.
This article shows you how to set up Emacs for VHDL work and make it behave like a regular Windows text editor
Microchip has announced the first FPGA to have a hard RISC-V IP CPU core; the PolarFire SoC. Read on to find out more. Update: There’s a dev board, too.