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Digital timing is probably the most critical aspect of FPGA design that newcomers face. It is taught in some Universities, but the importance of getting it right isn’t being stressed hard enough. I have seen a lot of engineers that don’t have a good grasp of the fundamentals of metastability or how to handle it properly.

If you get your digital timing wrong, your design can end up costing the company more money than it makes:
  • Field-recalls and unhappy customers
  • Time spent diagnosing problems that you can’t replicate

I recently updated the presentation that I gave in March 2018. You can download it from the link below.

DigitalTiming.pdf [0.91 MB]

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A long time ago, a colleague described the challenge of getting the widest data eye possible and some of the subtle things that he had to consider. He described what happens as a differential pair turned a corner; one of the two traces would always have to take a longer path. Here’s an example, below:

The problem here is not just that the outer trace is slightly longer than the inner one. What happens to the edge transitions as they propagate down the transmission line? Yuriy Shlepnev of Simberian Inc just posted a video which shown an animated example of exactly that.

If the transition on one trace gets too far ahead of the edge on the other trace, you will get cross-coupling from one to the other which will degrade both the rising and falling edges of the pair. You can correct the edge phase mismatch by adding a small jog-out in the trace with the shorter path close to the source (as shown below), but that causes an impedance discontinuity (and a small reflection). This may or may not be a problem, depending on the frequency that you are transmitting down the diff-pair, but it is worth being aware of.

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In August 2018, I presented a set of slides which should help engineers get to grips with the question: “What is Risc-V?”. It covers basics of the Risc-V family naming and gives an overview of how it’s implemented in hardware. It’s still fairly self-explanatory, so I’m putting it online without much more of an introduction. Get stuck in and feel free to contact me if you have comments.

RiscV_Starter.pdf [1.14 MB]

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Google offers a very interesting service which lets you plot a graph of how the world has searched for a particular term. Even better, you can plot a few terms against each other and see how they compare. It’s called Google Trends.

Some search terms are just not going to be useful. For example, I can’t compare the popularity of “Xilinx Vivado” against “Lattice Diamond” because the results get massively skewed with gemstone searches. Some queries work moderately well though. In 2017, I tried it out with terms like “Vivado” vs. “Quartus” and “VHDL” vs. “Verilog”. A sample is shown below.

This plot is for a 5 year period from 2012-2017 with “Xilinx” in blue and “Altera” in Red. What’s interesting is that you can clearly see the December holiday season. You can also see the spike of interest in “Altera” as Intel acquired them and that people are still searching for “Altera” over a year after Intel acquired them.

Take these results with scepticism and ask yourself why people search for things? Maybe it’s because it’s more popular (good), maybe it’s because it harder to use (bad), or maybe it’s something else entirely. I don’t pretend to have the answers.

I recently updated the presentation with results from March 2019. Has anything changed in 2 years? The full presentation is here:

FPGA_Trends_2019.pdf [1.00 MB]

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This presentation is aimed at beginners, so experienced engineers can ignore this post and move on. I am posting it because VHDL and Verilog are not like normal programming languages; instead of having a nice procession from one statement to another, everything happens at once (sort of).

This presentation shows how to read a simple design and describes how to synthesise the logic in your head. It is a key technique for getting the most out of some of the topics that I will be posting about later on.

How To Read VHDL.pdf [0.96 MB]

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