Metastability and Timing for Digital Logic


Digital timing is probably the most critical aspect of FPGA design that newcomers face. It is taught in some Universities, but the importance of getting it right isn’t being stressed hard enough. I have seen a lot of engineers that don’t have a good grasp of the fundamentals of metastability or how to handle it properly.

If you get your digital timing wrong, your design can end up costing the company more money than it makes:
  • Field-recalls and unhappy customers
  • Time spent diagnosing problems that you can’t replicate

I recently updated the presentation that I gave in March 2018. You can download it from the link below.

DigitalTiming.pdf [0.91 MB]