How To Read VHDL Code

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This presentation is aimed at beginners, so experienced engineers can ignore this post and move on. I am posting it because VHDL and Verilog are not like normal programming languages; instead of having a nice procession from one statement to another, everything happens at once (sort of).

This presentation shows how to read a simple design and describes how to synthesise the logic in your head. It is a key technique for getting the most out of some of the topics that I will be posting about later on.

How To Read VHDL.pdf [0.96 MB]

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