Automating The FPGA Build Flow

Posted

If you’ve designed for FPGA targets before, you’re probably familiar with using the GUI to point to your source code, set project parameters, synthesise and place & route your design.

What do you do if you want to tell someone exactly how you got from A to B? Do you remember every build option you selected for a file you made a week ago? What happens if someone asks you to repeat what you did, but on their machine? A “repeatability” problem exists between the keyboard and the chair; the human.

This presentation covers how you set up an FPGA project so that you can type “make” from the command-line and end up with a bitfile that you can upload to the FPGA.

AutomatingBuildFlow.pdf [0.18 MB]

Once you’ve automated your build process, you can point someone to the project’s make file and know they’ll be getting exactly the same build parameters that you have. You can also start looking at more advanced ways of building your projects, like setting up a continuous integration system.

Author
Categories ,

Comments

There are currently no comments on this article.

Would you like to leave a comment?

Enter your comment below. Fields marked * are required. You must preview your comment before submitting it.